Call: 508-541-8228
Home | About Us | Contact Us

FPGA Design Services

Tri-Star Design provides full turnkey FPGA design services and is experienced in both Verilog and VHDL. Our staff consists of experts in architecture, design, synthesis, verification, and test of FPGAs.

Whether your design requires a CPLD or one of the larger available FPGAs, Tri-Star Design has the talent and experience to design and develop an efficient design to meet your requirements. We utilize an HDL design process and support all the major FPGA and CPLD Vendors (Xilinx, Altera, Lattice). Tri-Star Design has been selected as a member of the Xilinx Alliance Program and as such members are entitled to access products, services, tools and discounts on items.

Tri-Star Design provides On-site and Turn-key FPGA Design Services. We work with your staff to deliver complex Veriolg/VHDL designs on a tight schedule.

Our expertise with all major FPGA devices and associated tool flow, High-level Hardware Verification Languages (HVL), combined with our strong understanding of popular bus protocols, peripherals and processor cores, help our clients improve confidence in quality of functional verification.

We provide On-site and Turn-key FPGA design services for our customers and we work with your staff to deliver complex Verilog/VHDL designs on a tight schedule. We can reduce time-to-market for you while providing a cost-effective solution. Tri-Star Design provides fixed price or hourly rate, team projects or individual assignments.

Our engineering expertise with all major FPGA devices and associated tool flow, High-level Hardware Verification Languages (HVL), combined with our strong understanding of popular bus protocols, peripherals and processor cores, help our clients improve confidence in quality of functional verification.

FPGA Design

  • RTL code generation (VHDL, Verilog)
  • High-speed interface design
  • Multiple clock domain design
  • Logic synthesis
  • Vendor functional macros
  • IP block integration

    FPGA Verification
  • Testbench generation
  • Functional simulation
  • Post-Synthesis simulation
  • Constrained random verification
  • Assertions

    FPGA Compilation and Analysis
  • Partitioning
  • Clock optimization
  • Design translation
  • Synthesis optimization
  • I/O planning and analysis
  • Static timing analysis
  • Design closure



  • © Tri-Star Design, Inc. || 34 Hayden Rowe Street, Suite 176 || Hopkinton, MA 01748 || Ph: 508-541-8228 || Fax: 508-541-4646